The present invention relates to a clock control circuit most suitable for a circuit subjected to synchronization control using a high-speed clock signal.
In recent years, a clock sync-type memory such as a synchronous DRAM has sometimes been used to meet the demand for a high processing speed of a computer system. Such a clock sync-type memory device uses an internal clock signal in synchronism with a clock signal input thereto for controlling the memory.
In the case where a delay occurs between the internal clock signal used in the memory device and an external clock signal input from an external source for controlling the memory device, the internal circuits of the memory device high in operating speed are liable to develop a malfunction even if the delay is small.
In view of this, a semiconductor integrated circuit such as a memory device using a clock signal includes a clock control circuit built in a memory integrated circuit for assuring synchronism between the internal clock signal and the external clock signal. First, the operating principle of this clock control circuit will be explained.
FIG. 1 shows a clock control circuit of synchronous adjustable delay (SAD) type including a synchronous traced backward delay (STBD) disclosed in U.S. Pat. No. 5,867,432 granted to Haruki Toda. This clock control circuit of SAD type is well known for its high sync speed and small power consumption. The contents of which are incorporated herein by reference in their entirely.
The circuit of FIG. 1 includes a clock receiver 11, a delay monitor circuit 12, a forward pulse delay circuit 14 having a plurality of delay circuits 13 connected in a multiplicity of stages in cascade, a backward pulse delay circuit 16 having delay circuits 15 connected in a multiplicity of stages in cascade in the same number as stages of the delay circuits 13 in the forward pulse delay circuit 14, and a state-hold section 18 having a plurality of state-hold circuits 17 as many as the delay circuits arranged in the forward pulse delay circuit 14 and the backward pulse delay circuit 16 for outputting a control signal for controlling the pulse delay operation in the backward pulse delay circuit 16 in accordance with the pulse delay state of the forward pulse delay circuit 14, a control signal generating circuit 19 for outputting control signals P, /P for controlling the operation of the forward pulse delay circuit 14 and the state-hold section 18, and a driver 20.
The output from the delay circuit 13 in the Nth stage in the forward pulse delay circuit 14 is input to the Nth-stage state-hold circuit 17 in the state-hold section 18, and the output from the Nth-stage state-hold circuit 17 in the state-hold section 18 is input to the (N-1)th-stage delay circuit 15 in the backward pulse delay circuit 16.
FIG. 2 is a timing chart for explaining the operating principle of the clock control circuit shown in FIG. 1. With reference to FIGS. 1 and 2, the operating principle of the conventional clock control circuit will be explained.
Now, assume that an external clock signal ExtCLK having a cycle of .tau. is input to the clock receiver 11. The external clock signal ExtCLK is shaped in waveform and amplified by the receiver 11 and output as a pulse signal CLK. In the case where a delay time in the clock receiver 11 is Trc, the pulse signal CLK is delayed by Trc behind the external clock signal ExtCLK, as shown in FIG. 2. The pulse signal CLK output from the receiver 11 is input to the delay monitor circuit 12, the control signal generating circuit 19 and the backward pulse delay circuit 16.
The control signal generating circuit 19 receives the pulse signal CLK, and as shown in FIG. 2, outputs a control signal P having a pulse width Wp in synchronism with the leading edge of the pulse signal CLK. Though not shown, the control signal generating circuit 19 outputs, together with the control signal P, a control signal /P having a level complementary with the control signal P. Where a delay time in the driver 20 is Tdr, the pulse width Wp of the control signal P is set shorter than the period (Trc+Tdr). The reason is that if the width Wp of the control signal P is longer than (Trc+Tdr), the output from the delay monitor circuit 12 fails to correctly propagate through the forward pulse delay circuit 14.
The delay monitor circuit 12 has a delay time (Trc+Tdr) equal to the sum of the delay time Trc in the receiver 11 and the delay time Tdr in the driver 20. Thus, the pulse signal FCL output from the delay monitor circuit 12, as shown in FIG. 2, is delayed by (Trc+Tdr) behind the pulse signal CLK output from the receiver 11 and input to the forward pulse delay circuit 14.
The forward pulse delay circuit 14 is configured with a plurality of delay circuits 13 connected in a multiplicity of stages in cascade. The delay circuit 13 in each stage transmits a forward pulse signal to the succeeding stage from the preceding stage when the control signal P is "L", while the transmission of the forward pulse signal is stopped when the control signal P is "H".
During the period {.tau.-(Trc+Tdr)} from the time point when the transmission is started of the pulse signal FCL through the forward pulse delay circuit 14 to the time when the control signal P rises to "H" level, the pulse signal FCL is transmitted through the forward pulse delay circuit 14.
The state-hold section 18 stores the transmission state of the forward pulse signal through the forward pulse delay circuit 14 in each state-hold circuit 17, and controls the operation of the backward pulse delay circuit 16 based on the information stored in the state-hold circuit 17 in such a manner that the transmission time of the backward pulse signal is equal to the transmission time of the forward pulse. Specifically, all the state-hold circuits 17 in the state-hold section 18 are initially reset. Those state-hold circuits 17 corresponding to the delay circuits 13 in the forward pulse delay circuit 14 to which the forward pulse signal is not transmitted remain reset as in their initial state.
The state-hold circuits 17 corresponding to the delay circuits 13 in the forward pulse delay circuit 14 to which the forward pulse signal is transmitted, on the other hand, are turned to set state. The control signal generated in accordance with the set/reset state of each state-hold circuit 17 is input to the backward pulse delay circuit 16.
The delay circuits 15 in the backward pulse delay circuit 16 controlled by the control signal from the state-hold circuit 17 corresponding to the set state output the backward pulse signal transmitted from the delay circuit 15 in the succeeding stage to the delay circuit 15 in the preceding stage.
The delay circuit 15 in the backward pulse delay circuit 16 controlled by the control signal from the state-hold circuit 17 corresponding to the reset state, on the other hand, outputs the pulse signal CLK output from the receiver 11 to the delay circuit 15 in the preceding stage.
When the control signal P changes to "H" level, the pulse signal CLK also changes to "H", and therefore the delay circuits 15 ((N+1)th and subsequent stages in FIG. 1) in the backward pulse delay circuit 16 controlled by the control signal from the state-hold circuit 17 in reset state are supplied with the "H" pulse signals CLK in parallel.
As shown in FIG. 1, assuming that there are N stages of the delay circuits 13 in the forward pulse delay circuit 14 through which the forward pulse signal is transmitted, the state-hold circuits 17 in the first to Nth stages of the state-hold section 18 are in set (S) state. As a result, the delay circuit 15 in the Nth stage in the backward pulse delay circuit 16 is controlled by the control signal from the state-hold circuit 17 in the (N+1)th stage of the state-hold section 18 in reset (R) state, and therefore the input pulse signal CLK is transmitted as a backward pulse signal to the delay circuit 15 in the preceding stage.
Consequently, the number of the delay circuits 15 through which the backward pulse signal is transmitted equals the number of stages of the delay circuits 13 in the forward pulse delay circuit 14 through which the forward pulse signal is transmitted.
Assume that each delay circuit in the forward pulse delay circuit 14 and the backward pulse delay circuit 16 is designed to have the same signal delay time. The pulse signal CLK input to the backward pulse delay circuit 16 is transmitted through the delay circuit 15 during the same period of {.tau.-(Trc+Tdr)} as in the case where the forward pulse signal is transmitted through the forward pulse delay circuit 14, and is output as a pulse signal RCL as shown in FIG. 2.
This pulse signal RCL is subsequently passed through the driver 20 and thus output as an internal clock signal IntCLK delayed by the period of Tdr.
Now, let .DELTA.total be the delay time from the time when the external clock signal ExtCLK is input to the time point when the internal clock signal IntCLK is output. Then, the time .DELTA.total is given as EQU .DELTA.total=.DELTA.msr+.DELTA.prp (1)
In equation (1), .DELTA.msr is the time during which the forward pulse signal is passed through several delay circuits 13 in the forward pulse delay circuit 14, and .DELTA.prp is the time required for the backward pulse to transmit through the delay circuits 15 in the backward pulse delay circuit 16 in the number corresponding to the number of the stages through which the forward pulse signal is transmitted and thereby to output the internal clock signal IntCLK.
As described above, the time Trc is required for the passage of the external clock signal ExtCLK through the receiver 11, the time (Trc+Tdr) is required for the passage of the pulse signal CLK through the delay monitor circuit 12, the time {.tau.-(Trc+Tdr)} is required for the passage of the pulse signal FCL through the forward pulse delay circuit 14, the time {.tau.-(Trc+Tdr)} is required for the passage of the pulse signal CLK through the backward pulse delay circuit 16, and the time Tdr is required for the passage of the pulse signal RCL through the driver 20. Thus, .DELTA.msr, .DELTA.prp in equation (1) are given as EQU .DELTA.msr=(Trc+Tdr)+{.tau.-(Trc+Tdr)}=.tau. (2) EQU .DELTA.prp=Trc+{.tau.-(Trc+Tdr)}.tau.+Tdr=.tau. (3)
Specifically, .DELTA.total is 2.tau., and therefore the internal clock signal IntCLK is synchronized in two cycles of the external clock signal ExtCLK, and remains in synchronism with the external clock signal ExtCLK from the third clock.
The external clock signal is known to contain a jitter. The jitter is defined as a variation of the period of the clock signal. The clock control circuit is required to operate normally even in the presence of a jitter in the external clock signal ExtCLK.
As shown in FIG. 3, for example, even in the case where the period of the external clock signal ExtCLK is shortened by .delta. as compared with the period .tau. one cycle before due to the jitter, the establishment of a synchronism requires that the backward pulse RCL is output by delaying the pulse signal CLK in the delay circuits 15 of the backward pulse delay circuit 16 in the number of stages corresponding to the delay circuits 13 in the forward pulse delay circuit 14 through which the transmission of the forward pulse signal is stopped. Specifically, the output pulse signal CLK from the receiver 11 corresponding to the external clock signal ExtCLK of the period (.tau.-.delta.) is required to be delayed by the period (.tau.-.delta.)-(Trc+Tdr) by the backward pulse delay circuit 16.
In one preceding cycle, however, the forward pulse signal is delayed by the period of .tau.-(Trc+Tdr) by the forward pulse delay circuit 14. Accordingly, the state-hold circuit 17 (two state-hold circuits 17 in FIG. 3) in the state-hold section 18 in the portion defined by dashed line in FIG. 3 is in set (S) state.
Thus, for the pulse signal CLK to be delayed by the period of (.tau.-.delta.)-(Trc+Tdr) by the backward pulse delay circuit 16 subsequently, the state-hold circuit 17 in the state-hold section 18 in the portion defined by dashed line in FIG. 3 is required to be restored from the set (S) state to the reset (S) state before starting the transmission of the forward pulse signal for the next cycle.
The trouble is that the clock control circuit shown in FIG. 1 cannot meet the required conditions when the duty cycle of the external clock signal reaches 50% or more.
Also, the specification of U.S. patent application Ser. No. 09/271,329 filed by Kamoshida et al. discloses a clock control circuit which eliminates the effect of the jitter contained in the external clock signal and which is capable of operation even in the case where the duty cycle of the external clock signal is not less than 50%. FIG. 4 is a block diagram showing a configuration of the clock control circuit disclosed in the specification of the particular patent application. The contents of which are incorporated herein by reference in their entirely.
Now, the configuration, function and the problem points of the circuit shown in FIG. 4 will be explained.
The clock control circuit shown in FIG. 4 is different from the circuit of FIG. 1 in that the clock control circuit of FIG. 4 further comprises a state-hold section reset circuit 21 and a control circuit 22 newly added thereto, that the pulse width of the pulse signal passed through the delay monitor circuit 12 can be adjusted in accordance with the control signal CTL output from the control circuit 22, and that the operation of the state-hold section 18 is controlled based on the control signals PM, /PM output from the control circuit 22 newly added.
The control circuit 22 outputs the control signals PM, /PM for controlling the operation of the state-hold section 18 in accordance with the backward pulse signal RCL and the control signals P, /P, and also outputs a control signal CTL for adjusting the pulse width of the pulse signal passed through the delay monitor circuit 12.
The control signal CTL is input to the delay monitor circuit 12. Based on this control signal CTL, the pulse width of the pulse signal output from the delay monitor circuit 12 is adjusted.
Now, the operation of the control circuit 22 will be explained with reference to the flowchart of FIG. 5.
In step S1, it is determined whether the backward pulse signal RCL is "H" or not when the control signal /P rises. In the case where the backward pulse signal RCL is "H", the process proceeds to step S2. In step S2, the control signal /PM is generated after the backward pulse signal RCL turns "L". In the case where the backward pulse signal RCL is "L", on the other hand, the process proceeds to step S3. In step S3, the control signal /PM in synchronism with the control signal /P is generated.
As long as the control signal /PM is "H", each state-hold circuit 17 in the state-hold section 18 is set to each output state based on the backward pulse signal transmitted through the forward pulse delay circuit 14.
Specifically, in steps S1 to S3, the level of the control signal /PM is set for controlling the operation of the state-hold section 18.
During the period when the control signal /PM is "H", the output signal of the state-hold circuit 17 corresponding to the delay circuit 13 in the forward pulse delay circuit 14 through which the forward pulse signal is transmitted is set to "H" level into a set state.
During the period when the control signal /PM is "L", on the other hand, the output signal of the state-hold circuit 17 corresponding to the delay circuit 15 in the backward pulse delay circuit 16 through which the backward pulse signal is transmitted is set to "L" level into a reset state.
The control flow of steps S4 to S6 in FIG. 5 is for obviating the new problem which otherwise might occur due to the control operation using the control signal /PM generated based on the preceding control flow of steps S1 to S3.
Thus, in the case where the control signal /PM generated in the control circuit 22 is in synchronism with the control signal /P, the delay monitor circuit 12 outputs the forward pulse signal FCL directly to the forward pulse delay circuit 14 as it is without extending the pulse width of the forward pulse signal FCL.
Even in the case where the control signal /PM is not in synchronism with the control signal /P, the pulse width of the pulse signal FCL output from the delay monitor circuit 12 is sometimes not required to be extended. In such a case, it is determined in step S4 whether the pulse signal RCL is "H" or not when the pulse signal FCL rises. In the case where the pulse signal RCL is "L", the pulse width of the pulse signal FCL is not required to be extended. After that, in step S6, the control signal CTL is generated to output the forward pulse signal FCL directly to the forward pulse delay circuit 14 as it is without extending the pulse width thereof.
In the case where the pulse signal RCL is "H" when the pulse signal FCL rises, on the other hand, the pulse width of the pulse signal FCL is required to be extended. After that, in step S5, the control signal CTL is generated in such a manner as to extend the pulse width of the forward pulse signal FCL.
In the case where the pulse width of the backward pulse signal is large, the circuit of FIG. 4 poses the following problem. Specifically, when the state-hold section 18 is reset by the state-hold section reset circuit 21, all the state-hold circuits 17 in the state-hold section 18 are set in reset state. As a result, once the input of the external clock signal ExtCLK is started, each delay circuit 15 in the backward pulse delay circuit 16 fetches the pulse signal CLK from the receiver 12 and transmits it to the delay circuit 15 in the preceding stage. As a result, as shown in FIG. 4, the output pulse signal CLK from the receiver 12 which has been input to the del ay circuit 15 in the first stage in the backward pulse delay circuit 16 is first delayed by the first-stage delay circuit 15 and output as a pulse signal RCL.
The clock signal having a period .tau. is required to be delayed by the period {.tau.-(Trc+Tdr)} by the backward pulse delay circuit 16. However the first backward pulse signal is transmitted only to the delay circuit 15 in the first stage. As shown in the timing chart of FIG. 7, therefore, the pulse signal RCL first output rises at a timing earlier than when it is normally output, and assumes a long pulse signal (RCL1 in FIG. 7) by being superposed on the pulse signal transmitted from the succeeding stage.
The backward pulse signal transmitted by the delay circuits in the succeeding stage of the backward pulse delay circuit 16 will be explained further with reference to FIG. 6.
As described earlier, concurrently with the output of the pulse signal RCL from the first-stage delay circuit 15, the transmission of the forward pulse signal is started by the forward pulse delay circuit 14. As a result, each state-hold circuit 17 in the state-hold section 18 corresponding to the delay circuit in the forward pulse delay circuit 14 through which the forward pulse signal is transmitted turns from reset to set state. Further, each delay circuit in the backward pulse delay circuit 16 corresponding to the state-hold circuit 17 in set state operates to transmit the backward pulse from the succeeding stage to the preceding stage.
As a result, as described earlier, the backward pulse signal sequentially transmitted from the succeeding stage is overlapped with the pulse signal output from the first stage, so that the pulse signal RCL1 first output comes to become a long pulse signal.
When this pulse signal RCL1 is input to the control circuit 22, as shown in the control flow of FIG. 5, the control circuit 22 generates a control signal CTL in such a manner as to extend the pulse signal FCL.
Thus, as shown in the timing chart of FIG. 7, the pulse width of the first pulse signal FCL (FCL1 in FIG. 7) is extended, and overlapped with the next pulse signal FCL. As a result, the internal clock signal IntCLK (the internal clock signal corresponding to the fourth clock of the external clock signal, i.e. IntCLK 3 in FIG. 7) established as the result of the pulse signal FCL of the second cycle being transmitted to the forward pulse delay circuit 14 ceases to be in synchronism with the external clock signal ExtCLK.
The failure of the internal clock signal corresponding to the fourth clock of the external clock signal as described above to be in synchronism with the external clock signal leads to the following inconveniences.
Specifically, the synchronous DRAM of double data rate (DDR) type in which the read data is output in synchronism with both the leading and trailing edges of the external clock signal has generally built therein the clock control circuit as described above. Also, in order to save the power consumption, it has the function of stopping the operation of the clock control circuit. This is commonly called the power down mode, and to leave this state is called "power down exit".
As an example of the power down mode, a timing chart for the active power down mode is shown in FIG. 8A, and a timing chart for the standby power down mode is shown in FIG. 8B. In FIGS. 8A, 8B, characters CKE designate an enable control signal for controlling the power down mode, and characters DQ the read data.
The active power down mode shown in FIG. 8A is the power down mode in the state in which any of the banks is selected (active state), and the standby power down mode shown in FIG. 8B is the power down mode in the state in which none of the banks is selected (non-active state). The "bank" is defined as a memory cell arrays independently operable and a control circuit therefor.
Specifically, when the enable control signal CKE turns "L", the power down mode is entered, while when the enable control signal CKE turns "H", the power down mode is left (power down exit).
In the active power down mode, the output of the data (DQ) is started from the fourth clock of the clock signal after starting to supply the external clock signal ExtCLK. Thus, the internal clock signal IntCLK output from the clock control circuit as a signal corresponding to the fourth clock is required to have the highest sync accuracy.
In the clock control circuit of FIG. 4 or 6, however, as described above, the internal clock signal out of synchronism with the external clock signal is output as the fourth clock of the external clock signal, and therefore the requirement of the data read operation of the highest sync accuracy cannot be met.
In order to assure a sync accuracy, therefore, it is necessary that the clock signal continues to be supplied at least to the clock control circuit even after the supply of the external clock signal is stopped according to the power down mode.
When the supply of the clock signal is stopped, it is desired to stop the operation of the clock control circuit by stopping the supply of the clock signal to the clock control circuit to thus reduce the power consumption to a remarkable degree. Nevertheless, due to the problem described above, the synchronous DRAM would develop a malfunction if the operation of the clock control circuit is stopped. Thus, in order to prevent such a malfunction, the operation of the clock control circuit cannot be stopped even when the supply of the clock signal is stopped.
Also, assume the standby power down mode in which data begins to be read during the standby period ready to receive a command while no bank is active. If the operation of the clock control circuit is stopped during the standby period, the fourth clock of the internal clock signal IntCLK incapable of being synchronized is used for the data read operation requiring the highest sync accuracy. For preventing the malfunction during the standby period, therefore, the operation of the clock control circuit cannot be stopped, thereby leading to the disadvantage that the power consumption cannot be reduced remarkably.
As described above, in the clock control circuit of FIG. 4 or 6, the internal clock signal fails to be synchronized with the external clock signal at the fourth clock after starting to supply the external clock signal. In spite of this, the internal clock signal (fourth clock) incapable of being synchronized is used for the operation requiring the highest sync accuracy. For this reason, in order to assure synchronism, at least the clock control circuit is required to be supplied with the clock signal to keep the clock control circuit in operation. Thus, although it is desired to stop the supply of the clock signal to the clock control circuit and thus to save the power consumption by deenergization of the clock control circuit, the problem pointed out above makes it impossible to stop the supply of the clock signal and thus to stop the operation of the clock control circuit.